An insulated gate bipolar transistor (IGBT), which is one of power semiconductor elements, is a power element that has the high-speed switching characteristics and voltage-driven characteristics of a metal oxide semiconductor field effect transistor (MOSFET) and the low on-voltage characteristics of a bipolar transistor. The application range of the IGBT extends from the industrial field including, for example, a general-purpose inverter, an AC servomechanism, an uninterrupted power supply (UPS), or a switching power supply to the consumer equipment field including a microwave oven, a rice cooker, or a strobe. In recent years, research has been conducted on a technique which provides a bidirectional switching element in a matrix converter, such as a direct-link-type conversion circuit, in order to perform alternating current (AC)/AC conversion, thereby reducing the size, weight, and costs of a circuit and increasing the efficiency and high-speed response of the circuit.
The bidirectional switching element can be simply configured by connecting reverse blocking IGBTs (RB-IGBTs) with a reverse voltage blocking capability that has the same high reliability as a forward voltage blocking capability in inverse parallel, which is preferable. However, the IGBT according to the related art has a high-reliability forward voltage blocking capability, but is generally designed and manufactured such that the reverse voltage blocking capability of the IGBT does not need to have the same level of reliability as the forward voltage blocking capability. Therefore, it is necessary to develop an IGBT (hereinafter, referred to as a reverse blocking IGBT) which is required to form the above-mentioned bidirectional switching element and has a reverse voltage blocking capability with the same level of reliability as the forward voltage blocking capability. The structure of the reverse blocking IGBT according to the related art will be described below. FIG. 2 is a cross-sectional view illustrating a main portion of a general reverse blocking IGBT according to the related art.
FIG. 2 is a cross-sectional view illustrating a main portion of the device structure of the reverse blocking IGBT. The layer structure of the reverse blocking IGBT illustrated in FIG. 2 differs from the layer structure of a general IGBT in that the reverse blocking IGBT includes a p-type isolation layer 2 which connects two opposite main surfaces with a diffusion layer of a conductivity type different from that of an n− substrate 1 in order to make the high-reliability reverse voltage blocking capability work effectively. The termination of a flat pn junction (hereinafter, referred to as a collector junction 8a) which is formed between an n− drift layer (n− substrate 1) and a p-type collector layer 8 provided on the rear surface side of the substrate and bears the reverse breakdown voltage is bent toward the front surface of the substrate and is extended to the surface of the edge termination structure portion 30 close to the front surface of the substrate by the p-type isolation layer 2 which surrounds the outer circumference of an active portion 20 and the edge termination structure portion 30. In this way, the pn junction can serve as a collector junction 8a which intersects the front surface of the substrate. In the surface of the edge termination structure portion 30 close to the front surface of the substrate, it is possible to effectively ensure both a high-reliability forward breakdown voltage and a high-reliability reverse breakdown voltage, using a junction termination surface protection mechanism using a field oxide film 14 and an electric field reduction mechanism including a field limiting ring 15 and a field plate 16. In FIG. 2, reference numeral 3a denotes a p-type base layer, reference numeral 4 denotes an n-type emitter layer, reference numeral 5 denotes a gate oxide film, reference numeral 6 denotes a gate electrode, reference numeral 7 denotes an emitter electrode, and reference numeral 8-1 denotes a collector electrode.
A general IGBT which is not a reverse blocking type is used in a circuit under a DC power supply and does not require a reverse voltage blocking capability. Therefore, the general IGBT does not require the p-type isolation layer and the wafer process is simplified. The general IGBT has an advantage in terms of costs. In addition, the termination of the collector junction which bears the reverse breakdown voltage of the general IGBT is generally exposed from the cut surface of the chip. Therefore, it may be said that the general IGBT has the structure in which the reliability of the reverse voltage blocking capability is low and is manufactured by a manufacturing method in which the reliability of the reverse voltage blocking capability is low from the beginning.
Next, the outline of a method for manufacturing the above-described reverse blocking IGBT according to the related art illustrated in FIG. 2 will be described with reference to FIGS. 3 to 8. FIGS. 3 to 8 are cross-sectional views illustrating an element of the general reverse blocking IGBT according to the related art which is being manufactured. The cross-sectional views which are referred to in the following description illustrate the schematic cross-section of a portion of a silicon substrate (hereinafter, simply referred to as a substrate in some cases) corresponding to an element (cell) of the IGBT and the end of a chip. In FIGS. 3 to 8, a plurality of cells in an active portion and an edge termination structure portion are not illustrated. First, a gettering polysilicon layer 1b with a thickness of 1.5 μm or less is deposited on the rear surface of an n-type silicon substrate 1a by a chemical vapor deposition (CVD) method and an opening portion 12 is formed in an initial oxide film 11 formed on a front surface 9 of the substrate (FIG. 3). A boron deposition region 13 is formed through the opening portion 12 by, for example, a coating diffusion method or an ion implantation method (FIG. 4). When the breakdown voltage is 1200 V, boron (B) drive diffusion is performed in an oxygen atmosphere at a high temperature of 1300° C. for a long time to change the boron deposition region 13 to the p-type isolation layer 2 with a depth of 200 μm (FIG. 5).
Then, the initial oxide film 11 is removed and a polysilicon gate electrode 6 is formed on the front surface of the substrate, with a gate oxide film 5 interposed therebetween. Then, a p base layer 3a is formed by boron ion implantation and necessary drive thermal diffusion, using the gate oxide film 5 and the polysilicon gate electrode 6 formed on the front surface of the substrate as a mask. Crystal defects which are caused by high-concentration oxygen introduced during the isolation diffusion are gettered to the gettering polysilicon layer 1b provided on the rear surface of the substrate by a heat treatment process in this stage and the density of the crystal defects in an operation region of the IGBT is reduced. Then, an n+ emitter layer 4 and a p+ collector layer 3b are formed in the p base layer 3a. Then, an emitter electrode 7 is formed on the polysilicon gate electrode 6, with an interlayer insulating film interposed therebetween, and a necessary pattern is formed on the surfaces of the n+ emitter layer 4 and the p+ collector layer 3b so as to come into ohmic contact therewith (FIG. 6).
Then, the rear surface of the n-type silicon substrate 1a is ground such that the n-type silicon substrate 1a has a wafer thickness (200 μm) corresponding to the breakdown voltage. In addition, mechanical polishing or chemical etching is performed on the rear surface of the n-type silicon substrate 1a such that the p-type isolation layer 2 is exposed from the ground rear surface 10 (FIG. 7). In this stage, the entire layer including a large number of crystal defects gettered to the rear surface of the substrate is removed by rear surface grinding. Reference numeral 1 denotes the n-type silicon substrate after the rear surface is ground.
Then, a p+ collector layer 8 is formed on the rear surface 10 of the n-type silicon substrate 1. The p+ collector layer 8 is electrically connected to the p-type isolation layer 2. A collector electrode 8-1 is formed so as to come into contact with the p+ collector layer 8 and the n-type silicon substrate 1 is diced at the center 2-1 of the p-type isolation layer 2 (FIG. 8). In this way, the reverse blocking IGBT according to the related art is manufactured.
As the method for manufacturing the semiconductor device using gettering, a method has been proposed in which a step of forming, as a gettering layer, a layer including crystal defects, which are formed by ion implantation of a rare gas element, on the rear surface of a substrate is performed before a semiconductor functional region forming process including a thermal treatment that is performed at a temperature of 1000° C. or higher, thereby reducing the influence of the crystal defects, which are caused by high-concentration oxygen introduced into the silicon substrate due to high-temperature long-term isolation diffusion, on breakdown voltage characteristics (for example, see the following Patent Document 1).
In addition, as another method for manufacturing the semiconductor device using gettering, the following method has been proposed: a p-type isolation layer is selectively formed in the upper surface of an n-type silicon substrate by diffusion; a p-type impurity diffusion layer is formed on the entire bottom of the n-type silicon substrate by diffusion at the same time as the p-type isolation layer is formed; and a portion of the silicon substrate surrounded by the p-type isolation layer is an element forming region. Therefore, it is possible to hold a bidirectional breakdown voltage and the p-type impurity diffusion layer can function as a crystal defect gettering layer. As a result, the manufacturing method can form a semiconductor device with high reliability, such as an IGBT (for example, see the following Patent Document 2).
Furthermore, as the method for manufacturing the semiconductor device using gettering, a method has been proposed which forms a gettering polysilicon layer with a thickness (film thickness) of 0.5 μm to 1.5 μm on the rear surface of a wafer in order to reliably remove a crystal defect, without reducing gettering capability, even when a high-temperature heat treatment, such as hydrogen annealing, is performed in a reducing atmosphere (for example, see the following Patent Document 3).
In addition, a gettering method using a polysilicon back seal according to the related art has been proposed in which a gettering function is not sufficient and it is difficult to prevent the breakdown of a gate oxide film of a MOS transistor (for example, see the following Patent Document 4).